This tutorial shows the use of an FPGA development board (Diligent Basys 3) to implement a pseudo-random generator and display the results on the 7-segment display. The additions in this project were to add a UART, Fifo, and a couple of FSM RTL modules to display the output on a Putty terminal. This project used Quartus Prime Lite 20.1 to develop the RTL and perform behavioral simulations. The final code was ported to Vivado and used to generate a bitstream for the Basys 3 board.
Links to examples in a Bitbucket repository are here: GitHub
Tutorial_Baysys_3_FPGA_Project_3