BLDC Control Part II
This blog continues the control loop development showing the outer loop. The input reference to the inner loop is a 60Hz clock (Fref1). The feedback is Fg/6 which is nominally ~60Hz. The overall control diagram is shown in Figure 7 with dotted lines outlining the inner loop which we covered earlier (see here) (Note: click figures to see detail).
Figure 7
The inner loop (Gin from Fref1 to Fg, including the motor) has a gain of unity and a low-pass response shown in Figure 8.
Figure 8
The outer loop will be comprised of the inner closed loop block (Figure 8) plus the Phase Detector, compensation, fractional divider and divide by N=6. The open loop equation for the outer loop is shown in equation 4.
Equation 4:Â Â
Compensation
For the phase error to settle at 0 the compensation, Gc(z), will need to have a pole at z=1. The compensation is chosen to be proportional + integral control, also called PI. The PI block will be implemented as the summation of the proportional gain plus the integral. This is done so that a limit can be applied to the error term and a limit for windup can be applied to the integrator at each sample. The difference equations for this is given below.
Equation 5:Â
The implementation was was done in fixed-point math with 6 fraction bits, refer to the Verilog code in module PI_comp.v.
Phase Detector
Near steady state the phase detector has a small signal gain of Fclk/Fref2. For an FPGA clock of 50MHz on this module and the input 60Hz the gain is Kpd=833333. Refer to the Verilog code in module phase_det.v
Fractional Divider
The fractional divider has a small signal gain of (Fg^2 / Fclk)/2^Nf. For n FPGA clock of 50MHz on this module and the Fg=360Hz and Nf=3 fractional bits the gain is Kfd = 0.000324. Refer to the Verilog code in module frac_divider.v.
The bode plot of the open loop system with a 1/60Hz sample rate is shown in Figure 9.
Figure 9
The gain margin is 31dB at 11.2Hz and the phase margin is about 82 deg at 1Hz. The closed loop response of the phase error is shown in figure 10.
Figure 10
With the compensation as designed the time to settle within 5% of a disturbance is about 200 samples or 3.3 sec. The scope trace repeated below shows Fg/6 on the green trace and Ref 60Hz on the bottom purple trace. The jitter between the edges is <10us peak-to-peak. Contributing to this could be noise on the analog Fg signal and or asymmetry in the magnetic centers of each of the 6 motor poles.
Scope Traces
The plot below is the phase error captured with an ILA in the FPGA. The clock is 50Mhz and the sample rate is 60 Hz, so the phase range can be +/- 833333. The capture was started while the motor was running then I put my handle on the polygon to take it out of lock. Then I released the motor and let it settle. The sample rate is 60Hz so each major division below is 200 samples == 3.33 sec. Between sample 0 and 300 the motor was locked with no brake applied and the phase error was near zero. From about sample 300 to 425 the brake was applied and the phase error slips between [0, -8333333] modulo 2*pi. After about sample 425 the brake was removed, and the phase error reduced stably from ~400000 to around 0 in 200 samples or 3.33 sec.
Figure 11
Closing
This completes the design of the digital phase locked loop for accurate phase using the TI DRV10866 motor driver. This implementation is comprised of an inner velocity loop and an outer phase locked loop. The code for this project is available upon request.