MCU Phase Detector using DMA in the STM32F303RE

In an earlier blog I described a BLDC motor control using a phase detector (PD) implemented in an FPGA, along with the other closed loop compensation. In this blog I will describe a similar control loop but instead implemented in a STM32F303RE MCU. The challenge in this design is to move all control internal to the MCU and to not use any peripheral logic in the FPGA. The key performance specification for this design is to achieve less than 3 usec peak-to-peak jitter in the once around optical feedback. A block diagram of the system is shown in Figure 1. The inner velocity control loop is implemented using the Field Oriented Control (FOC) library from the ST tools. The outer loop is the PD with PID compensation. In this case the outer loop PID function will use the ST library. This blog will focus on the implementation of the PD. My intention is to help those just getting started with the STM32 and it's tools. Those wanting a copy of the MXCube *.ioc file can contact me.

Why The Choice of DMA

The critical timing in the design is the measurement of phase between the reference and feedback without introducing measurement jitter. The choices within the MCU are software polling, interrupts and DMA. It should be obvious that given our jitter requirement the use of software polling is not considered.

In the system the motor is using 16kHz PWM and making ADC acquisitions both of which are occurring with high priority interrupts. Any interrupt scheme used for the PD would incur the latency of getting into and out of the interrupt (24 clocks total) plus the computation time in the higher priority interrupt. The interrupts for a PD could easily see a 15-30usec peak-peak jitter. For this reason the use of interrupts for the PD measurement are avoided.

It may seem like overkill to use DMA to capture a single 32-bit word but the accuracy is ideal for this application. Two DMA channels are used to capture a free running timer. The capture occurs on the rising edge of the incoming signal and the capture is accomplished in hardware, independent of the MCU Core activity. Once the timer captures are accomplished any delay in processing is simply a system delay and not a contributor to measurement jitter.

Implementation

The project was created using STMicroelectronics STM32CubeMx v5.6.1 and the Keil Tool chain. Note the size of the code exceeds the 32k limit of the 'free' Keil compiler. In addition to the code which the 'Cube' creates the user must add some initialization code. The hardware platform used is the STM32 Nucleo-F303RE MCU board plus the Nucleo Expansion IHM16M1 Driver board.

In this example Timer4 is used as the PD timer. Timer1 is dedicated to the FOC motor control.

Figure 1 shows the interconnect of the Timer4 sections to implement the phase detector.

Figure 1 - Timer Peripherals for Phase Detector 

I configured Timer4 to have a 72MHz clock with a prescale of 8 (divide by 9) giving a resolution of 125ns. The divider is chosen as 65535 to give a rollover rate of 137.3Hz. This is chosen to be considerably less than the nominal 192Hz motor reference frequency. For MCU specifics use the ST Reference Manual RM0365.

Timer4 channel 1 is used to capture the reference frequency and Timer4 channel 2 is used to capture the feedback frequency. The peripheral interconnects of the STM32F303RE are such that these particular timer captures can be connected to DMA1 channel 1 and DMA1 channel 4 respectively. The DMA channels are each configured as a single word operating in circular buffer mode.

In software DMA1 channel 1 destination address is assigned to uint32_t buffer1 and DMA1 channel 4 is assigned to uint32_t buffer2. The source address for the DMA channels is the peripheral address of the Timer4 capture registers CCR1 and CCR2.

The gist snippet below shows the main.c module. The areas of interest are the DMA configuration in the call to user function DMA_Config before entering the while loop and the enabling of Timer 4. Also of interest are the functions MX_Timer4_Init and phase_detect.

The second snippet from file stm32f3xx_it.c  shows the transfer complete interrupt handlers that do the processing after the data is captured.

from file stm32f3xx_it.c,

Test Results

As a test the two inputs were connected together and driven with a pulse generator at 200Hz with a 50% duty cycle. The inputs are setup to both trigger on rising edges. In this mode it represents the two phase inputs being perfectly in phase. The result was the phase error (ph_error) reported on every sample was zero (0).

The second test was the same setup but changes the polarity of the fbk channel to trigger on the negative edge. The figure below shows the setup. Normally Ch1 and Ch2 inputs would be the two waveforms in panel (a) with the timer triggering on the rising edges. For this test we setup panel (b) with one waveform going to both channels. One channel triggers on the rising edge and the other channel on the falling edge. The red arrows indicate the resulting phase error magnitude.

Figure 2 - Test setup waveforms

In this setup changing the duty cycle directly adjusts the phase. I used the pulse generator set to a period of 1/200Hz and varied the pulse width. The table below is the pulse width (dt) and the measured phase error in clock counts. In this case the phase error was negative and it increased linearly to the maximum limit, PHASE_MAX, of 20000 counts. The resolution is 125ns.