This tutorial shows the use of an FPGA development board (Diligent Basys 3) to implement a pseudo-random generator and display the results on the 7-segment display. The approach used in this project shows the use and advantages of using Vivado Block Design. The end result is the same but the work-flow used was different than in project #1 which used only RTL modules.
Links to examples in a Bitbucket repository are here: GitHub
Tutorial_Baysys_3_FPGA_Project_2